Design and Evaluation of a 32-bit Carry Select Adder using 4-bit Hybrid CLA Adder

Adder circuits play a remarkable role in modern microprocessor. Adders are widely used critical paths of arithmetic operation such as multiplication and subtraction. A Carry Select (CSA) design methodology using modified 4-bit Look-Ahead (CLA) has been proposed this research. The CLA hybrid logic style based for Generate (Gi) Propagate (Pi) functions order to improve performance reduce the number transistor used. is basic unit implementation 32-bit CSA. CSA compared with conventional static CMOS Ripple Cary (RCA) by conducting simulation Cadence Virtuoso. Power consumption delay found 322.6 (uW) 0.556 (ns) whereas power was 455.4 0.667 respectively. We have done all Virtuoso 90 nm tool.